In chip-multiprocessors (CMP) architecture, the L2 cache is shared by the L1 cache of each processor core, resulting in a high\nvolume of diverse data transfer through the L1-L2 cache bus. High-performance CMP and SoC systems have a significant amount\nof data transfer between the on-chip L2 cache and the L3 cache of off-chip memory through the power expensive off-chip memory\nbus. This paper addresses the problem of the high-power consumption of the on-chip data buses, exploring a framework for\nmemory data bus power consumption minimization approach. A comprehensive analysis of the existing bus power minimization\napproaches is provided based on the performance, power, and area overhead consideration. A novel approaches for reducing the\npower consumption for the on-chip bus is introduced. In particular, a serialization-widening (SW) of data bus with frequent value\nencoding (FVE), called the SWE approach, is proposed as the best power savings approach for the on-chip cache data bus. The\nexperimental results show that the SWE approach with FVE can achieve approximately 54% power savings over the conventional\nbus for multicore applications using a 64-bit wide data bus in 45 nm technology.
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